Minesh Patel

Assistant Professor of Computer Science

Rutgers University

	minesh.patelh@gmail.com
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Hi, I'm Minesh! I recently joined Rutgers University as an assistant professor in CS (S'24). Prior to that, I completed my Ph.D. at ETH Zürich in the SAFARI research group.

I take an analytical approach to designing robust computer architectures and systems. My work combines new hardware-software mechanisms, test methodologies, and analysis techniques to address robustness challenges with a focus on the intersection of different system components.

I'm actively seeking new students! If you're excited to work with me, please reach out by e-mail.

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Teaching

CS 672: System Reliability at Scale [Spring 2024]

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Research Interests

I am broadly interested in the intersection between computer architecture, systems, and dependability, including:

• Architectures, programming interfaces, and runtime support for highly-efficient, cost-effective dependable systems capable of adapting to moving dependability goals (e.g., security, reliability, maintainability, etc.).
• Device and system design guidelines (e.g., standards, specifications) that facilitate transparency and informed decision-making during system design, analysis, modeling, and evaluation.
• System optimizations, mechanisms, and techniques to provide architectural, runtime and/or application control over how security and reliability concerns are addressed (e.g., prediction, detection, mitigation).

My dissertation targets memory systems reliability — specifically, addressing DRAM technology scaling challenges, including DRAM refresh overheads and growing single-bit error rates. The dissertation contributes new techniques for understanding and identifying how errors manifest in modern DRAM chips, thereby enabling informed decision-making during system design. Here is a recent talk I delivered summarizing my dissertation work, for which I am honored to be awarded the William C. Carter PhD Dissertation Award in Dependability.

Beyond my dissertation, I have research experience in a broad range of topics related to the memory system, including rethinking hardware and/or software to enable new functionality (e.g., virtual memory abstractions, in-memory computation, security primitives) and improve system-level metrics such as performance, energy-efficiency, and security.

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Education and Experience

I started my Ph.D. at Carnegie Mellon in 2015 and moved to ETH Zürich along with my adviser in 2017. Before that, I did my undergrad at UT Austin in both physics and electrical engineering.

I have substantial industry experience in the form of internships both before and during my Ph.D. During my Ph.D., I had (1) three research internships with Apple's Platform Engineering and SEG DRAM teams; and (2) one with Microsoft Research's Mobility and Networking Group. Before my Ph.D., I (1) worked with Apple's SEG Graphics team; (2) National Instruments R&D's Digital Design team; and (3) General Electric's UNIX/Linux Engineering team.

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Awards

• ETH Zürich Medal for Outstanding Doctoral Theses

  My graduate dissertation has been honored with a Silver Medal of ETH Zurich nominated by the Department of Information Technology and Electrical Engineering (D-ITET).

  [award announcement (ETH/news item)]




• William C. Carter PhD Dissertation Award in Dependability

  My graduate dissertation work has been recognized for "a significant contribution to the field of dependable computing" by the IEEE TCFT and IFIP WG 10.4.

  [acceptance speech at DSN 2022 (pdf/pptx/video)]




• ISCA Hall of Fame

  Thanks to the combined efforts of our work during my time in the SAFARI research group, I have the honor of (possibly being the first) to have entered the ISCA hall of fame before having defended my Ph.D.




• Best Paper Award for Patel et al., MICRO'20

  This work introduces BEER, a new memory testing technique capable of systematically determining the details of the error-correcting code used within a DRAM chip (i.e., on-die ECC). We demonstrate BEER's correctness and practicality using a combination of real-chip and simulation-based experiments and release an open-source tool, BEER, to enable applying BEER to other DRAM chips.




• Best Paper Award for Patel et al., DSN'19

  This work introduces EIN, a statistical inference methodology that uses MAP estimation to infer hidden details of both (1) the error-correcting code used within a memory chip; and (2) raw bit error characteristics. We demonstrate EIN in practice by applying it to real LPDDR4 DRAM chips and release an open-source tool, EINSim, to enable applying EIN to other DRAM chips.

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Publications

Please also see my Google Scholar page.

Refereed Conference Publications

1. Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices

   G. Yaglikci, H. Luo, G. F. de Oliviera Jr., A. Olgun, Minesh Patel, J. Park, H. Hassan, J. S. Kim, L. Orosa, and O. Mutlu

   IEEE/IFIP International Conference on Dependable Systems and Networks (DSN-52), Jun. 2022

   [paper (pdf/arxiv) | talk (pdf/pptx)]

2. HARP: Practically and Effectively Identifying Uncorrectable Errors in Main Memory Chips That Use On-Die ECC

   Minesh Patel, G. F. de Oliveira Jr., O. Mutlu

   ACM Stamps for Full Artifact Evaluation

   International Symposium on Microarchitecture (MICRO-54), Oct. 2021

   [paper (pdf/arxiv) | talk (pdf/pptx/video) | lightning talk (pdf/pptx/video) | source code (GitHub)]

3. A Deeper Look into RowHammer's Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses

   L. Orosa, G. Yaglikci, H. Luo, A. Olgun, J. Park, H. Hassan, Minesh Patel, J. S. Kim, O. Mutlu

   International Symposium on Microarchitecture (MICRO-54), Oct. 2021

   [paper (pdf/arxiv) | talk (pdf/pptx/video) | lightning talk (pdf/pptx/video)]

4. QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips

   Ataberk Olgun, Minesh Patel l, A. Giray Yaglikci, Haocong Luo, Jeremie S. Kim, F. Nisa Bostanci, Nandita Vijaykumar, Oguz Ergin, and Onur Mutlu

   International Symposium on Computer Architecture (ISCA-48), Jun. 2021

   [paper (pdf/doi/arxiv) | full talk (pdf/pptx/video) | short talk (pdf/pptx) | lecture (video)]

5. CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations

   Lois Orosa, Yaohua Wang, Mohammad Sadrosadati, Jeremie S. Kim, Minesh Patel, Ivan Puddu, Haocong Luo, Kaveh Razavi, Juan Gomez-Luna, Hasan Hassan, Nika Mansouri-Ghiasi, Saugata Ghose, and Onur Mutlu

   International Symposium on Computer Architecture (ISCA-48), Jun. 2021

   [paper (pdf/doi/arxiv) | full talk (pdf/pptx/video) | short talk (pdf/pptx)]

6. SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM

   Nastaran Hajinazar, Geraldo F. Oliveira, Sven Gregorio, Joao Dinis Ferreira, Nika Mansouri Ghiasi, Minesh Patel, Mohammed Alser, Saugata Ghose, Juan Gomez-Luna, and Onur Mutlu

   International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-26), Mar.-Apr. 2021

   [paper (pdf/doi/arxiv) | full talk (pdf/pptx/video) | short talk (pdf/pptx/video) | extended abstract (pdf)]

7. BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows

   A. G. Yaglikci, Minesh Patel, J. S. Kim, R. Azizi, A. Olgun, L. Orosa, H. Hassan, J. Park, K. Kanellopoulos, T. Shahroodi, S. Ghose, and O. Mutlu

   International Symposium on High-Performance Computer Architecture (HPCA-27), Feb. 2021

   [paper (pdf/doi/arxiv) | full talk (pdf/pptx/video) | short talk (pdf/pptx/video)]

8. Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

   Minesh Patel, J. S. Kim, T. Shahroodi, H. Hassan, and O. Mutlu

   International Symposium on Microarchitecture (MICRO-53), Oct. 2020

   Best Paper Award

   [paper (pdf/doi/arxiv) | full talk (pdf/pptx/video) | lightning talk (pdf/pptx/video) | short talk (pdf/pptx/video) | lecture (pdf/pptx/video) | source code (GitHub)]

9. FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching

   Y. Wang, L. Orosa, X. Peng, Y. Guo, S. Ghose, Minesh Patel, J. S. Kim, J. G. Luna, M. Sadrosadati, N. M. Ghiasi, and O. Mutlu

   International Symposium on Microarchitecture (MICRO-53), Oct. 2020

   [paper (pdf/doi/arxiv) | full talk (pdf/pptx/video) | lightning talk (pdf/pptx/video) | short talk (pdf/pptx/video) | lecture (pdf/pptx/video)]

10. Revisiting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques

    J. S. Kim, Minesh Patel, A. G. Yaglikci, H. Hassan, R. Azizi, L. Orosa, and O. Mutlu

    International Symposium on Computer Architecture (ISCA-47), Jun. 2020

    [paper (pdf/doi/arxiv) | full talk (pdf/pptx/video) | lightning talk (pdf/pptx/video) | poster (pdf/pptx) | lecture (pdf/pptx/video)]

11. CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off

    H. Luo, T. Shahroodi, H. Hassan, Minesh Patel, A. G. Yaglikci, L. Orosa, J. Park, and O. Mutlu

    International Symposium on Computer Architecture (ISCA-47), Jun. 2020

    [paper (pdf/doi/arxiv) | full talk (pdf/pptx/video) | lightning talk (pdf/pptx/video)]

12. The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework

    N. Hajinazar, P. Patel, Minesh Patel, K. Kanellopoulos, S. Ghose, R. Ausavarungnirun, G. F. de Oliveira Jr., J. Appavoo, V. Seshadri, and O. Mutlu

    International Symposium on Computer Architecture (ISCA-47), Jun. 2020

    [paper (pdf/doi/arxiv) | full talk (pdf/pptx/video) | lightning talk (pdf/pptx/video) | poster (pdf/pptx) | lecture (video)]

13. Are We Susceptible to Rowhammer? An End-to-End Methodology for Cloud Providers

    L. Cojocar, J. S. Kim, Minesh Patel, L. Tsai, S. Saroiu, A. Wolman, and O. Mutlu

    IEEE Symposium on Security and Privacy (S&P-41), May 2020

    [paper (pdf/doi/arxiv) | full talk (pdf/pptx/video)]

14. CROW: A Low-Cost Substrate for Improving DRAM Performance, Energy Efficiency, and Reliability

    H. Hassan, Minesh Patel, J. S. Kim, A. G. Yaglikci, N. Vijaykumar, N. M. Ghiasi, S. Ghose, and O. Mutlu

    International Symposium on Computer Architecture (ISCA-46), Jun. 2019

    [paper (pdf/doi) | full talk (pdf/pptx/video) | lightning talk (pdf/pptx/video) | poster (pdf/pptx) | source code (GitHub) | lecture (video)]

15. CoNDA: Efficient Cache Coherence Support for Near-Data Accelerators

    A. Boroumand, S. Ghose, Minesh Patel, H. Hassan, B. Lucia, R. Ausavarungnirun, K. Hsieh, N. Hajinazar, K. T. Malladi, H. Zheng, and O. Mutlu

    International Symposium on Computer Architecture (ISCA-46), Jun. 2019

    [paper (pdf/doi) | full talk (pdf/pptx) | lightning talk (pdf/pptx/video) | poster (pdf/pptx)]

16. Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices

    Minesh Patel, J. S. Kim, H. Hassan, and O. Mutlu

    IEEE/IFIP International Conference on Dependable Systems and Networks (DSN-49), Jun. 2019

    Best Paper Award

    [paper (pdf/doi) | full talk (pdf/pptx/video) | source code (GitHub) | lecture (video)]

17. D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput

    J. S. Kim, Minesh Patel, H. Hassan, L. Orosa, and O. Mutlu

    International Symposium on High-Performance Computer Architecture (HPCA-25), Feb. 2019

    IEEE Micro Top Picks Honorable Mention

    [paper (pdf/doi) | full talk (pdf/pptx/video) | lecture (video)]

18. Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration

    Y. Wang, A. Tavakkol, L. Orosa, S. Ghose, N. M. Ghiasi, Minesh Patel, J. S. Kim, H. Hassan, M. Sadrosadati, and O. Mutlu

    International Symposium on Microarchitecture (MICRO-51), Oct. 2018

    [paper (pdf/doi) | full talk (pdf/pptx/video) | lightning talk (pdf/pptx/video) | poster (pdf/pptx)]

19. Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local Bitlines

    J. S. Kim, Minesh Patel, H. Hassan, and O. Mutlu

    IEEE International Conference on Computer Design (ICCD-36), Oct. 2018

    [paper (pdf/doi) | full talk (pdf/pptx/video)]

20. The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern DRAM Devices

    J. S. Kim, Minesh Patel, H. Hassan, and O. Mutlu

    International Symposium on High-Performance Computer Architecture (HPCA-24), Feb. 2018

    [paper (pdf/doi) | full talk (pdf/pptx/video) | lightning talk (pdf/pptx/video)]

21. The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions

    Minesh Patel, J. S. Kim, and O. Mutlu

    International Symposium on Computer Architecture (ISCA-44), Jun. 2017

    [paper (pdf/doi) | full talk (pdf/pptx) | lightning talk (pdf/pptx)]

Refereed Journal Publications

1. LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory

   A. Boroumand, S. Ghose, Minesh Patel, H. Hassan, B. Lucia, K. Hsieh, K. T. Malladi, H. Zheng, and O. Mutlu

   IEEE Computer Architecture Letters (IEEE CAL), Jun. 2017

   [paper (pdf/doi/arxiv)]

Ongoing Work

1. A Case for Transparent Reliability in DRAM Systems

   Minesh Patel, T. Shahroodi, A. Manglik, G. Yaglikci, A. Olgun, H. Luo, and O. Mutlu

   arXiv, Apr. 2022

   [paper (arxiv) | open-source dataset (GitHub)]

Doctoral Dissertation

1. Enabling Effective Error Mitigation In Memory Chips That Use On-Die Error-Correcting Codes

   Minesh Patel

   Ph.D. Dissertation, ETH Zürich, Apr. 2022

   [thesis (ETH Library/arxiv) | defense slides (pdf/pptx)]

   William C. Carter PhD Dissertation Award in Dependability

   [award (website) | acceptance speech (pdf/pptx/video) | SAFARI news (article)]

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Talks

1. Reshaping DRAM Scaling by Enabling System-Memory Cooperation

   ETH Züirch, Switzerland. Oct. 2023

   SAFARI Live Seminar (website)

   [full talk (video)]

2. Acceptance Speech: William C. Carter PhD Dissertation Award in Dependability

   Baltimore, MD, USA. Jun. 2022

   IEEE/IFIP International Conference on Dependable Systems and Networks (DSN-52)

   [talk (pdf/pptx/video)]

3. HARP: Practically and Effectively Identifying Uncorrectable Errors in Main Memory Chips That Use On-Die ECC

   Virtual, Oct. 2021

   International Symposium on Microarchitecture (MICRO-54)

   [talk (pdf/pptx/video) | lightning talk (pdf/pptx/video)]

4. Enabling Effective Error Mitigation in Memory Chips that Use On-Die Error-Correcting Codes

   Virtual, Sep. 2021

   SAFARI Live Seminar (website)

   [full talk (video)]

5. Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

   Virtual, Oct. 2020

   International Symposium on Microarchitecture (MICRO-53)

   [full talk (pdf/pptx/video) | lightning talk (pdf/pptx/video) | short talk (pdf/pptx/video) | lecture (pdf/pptx/video)]

6. Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices

   Potland, OR, USA, Jun. 2019

   IEEE/IFIP International Conference on Dependable Systems and Networks (DSN-49)

   [talk (pdf/pptx/video)]

7. The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions

   Toronto, Canada, Jun. 2017

   International Symposium on Computer Architecture (ISCA-44)

   [full talk (pdf/pptx) | lightning talk (pdf/pptx)]